1. Field of the Invention
The present invention relates to a loop system for a voltage-controlled oscillator and related method, and more particularly, to a loop system having a plurality of frequency operating curves capable of auto-calibrating an oscillating frequency range and related method.
2. Description of the Prior Art
In an electronic device, clock signal synthesis and system synchronization are critical issues influencing accuracy of signal processing. For example, in a mixed signal system, an analog-to-digital (A/D) converter demands a low-jitter clock signal for sampling signals. In a wireless communications system, such as a Bluetooth or Global system for mobile communications (GSM) system, a radio frequency (RF) circuit requires a frequency synthesizer to generate carrier signals so as to transmit a baseband signal in a higher frequency band. In general, the foregoing applications adopt a phase-locked loop circuit for a stable and precise clock signal.
A phase-locked loop locks a phase difference between a periodic output signal and a periodic input signal through a feedback mechanism so as to stabilize a clock signal. Please refer to FIG. 1, which depicts a schematic diagram of a phase-locked loop (PLL) circuit 100 according to the prior art. The PLL circuit 100 includes a reference divider 102, a phase/frequency detector (PFD) 104, a charge pump 106, a loop filter 108, a voltage-controlled oscillator (VCO) 110 and a feedback divider 112. As can be seen from FIG. 1, the reference divider 102 divides a frequency of an input signal FIN to obtain a reference signal FREF. The PFD 104 is responsible for comparing a phase of the reference signal FREF with that of a feedback signal FFB to generate an error signal. When the reference signal FREF leads the feedback signal FFB in phase, the error signal is an up signal; when the reference signal FREF lags the feedback signal FFB in phase, the error signal is a down signal. A pulse width of the error signal indicates a phase difference between the reference signal FREF and the feedback signal FFB. According to the error signal, the charge pump 106 generates a specific electric charge for adjustment of the loop filter 108. When the error signal is outputted as the up signal, the charge pump 106 adds the electric charge to the loop filter 108. On the contrary, when the error signal is outputted as the down signal, the charge pump 106 withdraws the electric charge from the loop filter 108. The loop filter 108 is commonly a simple RC circuit functioning as an integrator, and is used for storing electric charge from the charge pump 106. The VCO 110 generates a periodic output signal FOSC when an output voltage VC of the loop filter 108 is inputted to the VCO 110. The feedback divider 112 performs division on frequency of the output signal FOSC to generate the feedback signal FFB. Thus, a phase-locked loop L1 is established. In general, the VCO 110 outputs a higher frequency range than the input signal FIN does, so that frequency of the output signal FOSC is a mixed fraction or a multiple of frequency of the input signal FIN. Thus, by adjusting a dividing factor of the reference divider 102 and the feedback divider 112, the PFD 104 can operate in a lower frequency range, so that likelihood of phase-comparison errors in the PFD 104, such as dead zone, can be decreased.
As mentioned above, the PLL circuit 100 can adjust an operating frequency of the VCO 110 by comparing the phase of the reference signal FREF with that of the feedback signal FFB continuously. The VCO eventually locks at a resulting frequency, which is extremely close to or right on the target frequency, and the output signal FOSC is regarded as a clock signal. For example, in a GSM 900 system, the physical layer of the network system uses a frequency band centralized at 900 MHz, and bandwidth of every carrier is defined to be as wide as 200 KHz. When a transmitter needs to transmit signals in a higher frequency band, the PLL circuit 100 converts the reference signal FREF to a 200 KHz periodic signal by setting the dividing number of the reference divider 102. And, since 900M is 4500 times 200K, the dividing factor of the feedback divider 112 should be set to 4500. The PLL circuit 100 continuously compares the phase of the reference signal FREF with the phase of the feedback signal FFB. The feedback signal FFB is persistently adjusted by the VCO 110 to increase its frequency to 900 MHz so that the baseband signal is up-converted to the high frequency band.
Generally, the VCO 110 shown in FIG. 1 is designed for applications operating in a large operating frequency range such as a commonly used range from 40 kHz to 400 MHz. However, the larger operating frequency range a frequency operating curve of the VCO 110 covers, the more noise will be generated in the PLL circuit 100. In order to reduce noise in the PLL circuit 100, a gain of the VCO 110 is required to be sufficiently small. That is to say, a slope of the frequency operating curve of the VCO 110 should be gentle. Thus, to achieve both a large operating frequency range and low-noise operation, the VCO 110 is usually designed to have a plurality of operating curves having gentle slopes. Each of the operating curves is a function of input voltages, as shown in FIG. 2. Based on a variety of applications, the PLL circuit 100 has to use different operating frequency ranges, so a specific frequency operating curve is selected for the VCO 110 to operate. Ideally, the VCO 110 designed in the same architecture should have the same central frequency and the same curve slopes in their frequency operating curves. As a result, each PLL 100 just chooses the same, fixed frequency range for the VCO 110 for a specific application. However, in practice, the characteristics (range coverage) of frequency operating curves may vary from VCO 110 to VCO 110 due to potential variations in fabrication of the VCO. For example, the frequency operating curves shown in the FIG. 2 may jointly be shifted up, down, left or right from VCO 110 to VCO 110. Moreover, the frequency operating curves may even have different slopes. As a result, for some applications, the VCO 110 of the PLL 100 needs a control signal to select a frequency range appropriate for the desired output frequency.
Conventionally, every VCO 110 is tested in the factory to characterize the frequency ranges and to predetermine which control signal matches the desired output frequency. As for a specific application for use with the VCO 110, appropriate control settings are permanently burned into the VCO device by blowing fuse links or hard-wiring. Therefore, in the prior art, the factory testing process and hard-wiring of the VCO 110 increase the cost of manufacturing the PLL. The frequency range of the prior art PLL is also limited to a permanently predetermined frequency range.